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DARPA invests $1.4 billion to build multi-chiplet 3D processors for military and civilian applications

DARPA has selected the Texas Institute for Electronics (TIE) at The University of Texas (UT) at Austin to develop 3D-integrated multi-chiplet advanced ‘semiconductor microsystems’ for the U.S. Department of Defense. This project involves creating a national R&D and prototyping facility to produce high-performance, energy-efficient, lightweight, and compact defense systems. A $1.4 billion projectThe project is part of DARPA’s Next Generation Microelectronics Manufacturing (NGMM) program, which aims to design 3D packaging technologies and build appropriate facilities for military and civil use. The project involves a $1.4 billion investment, with DARPA contributing $840 million and the Texas Legislature pouring in another $552 million in TIE.  This funding will be used to modernize two UT fabrication facilities that are set to foster dual-use innovations in the 3DHI multi-chiplet integration for both the defense sector and the semiconductor industry. These facilities will be self-sustained and accessible to academia, industry (including startups), and government. The program spans two phases, each lasting 2.5 years. In the first phase, TIE will focus on building the center’s infrastructure and foundational capabilities. The second phase will involve creating 3D-integrated (3DHI) hardware prototypes crucial to the DoC and automating various processes. Additionally, TIE will collaborate with DARPA on other separately funded design challenges.  “By investing in leading-edge microelectronics manufacturing, we are helping secure this vulnerable supply chain, boosting our national security and global competitiveness, and driving innovation in critical technologies,” said U.S. Sen. John Cornyn. “The next generation of high-performing semiconductors these resources will enable through DARPA’s partnership with UT TIE will help not only bolster our defense but also pave the way for the U.S. to reclaim its leadership role in this critical industry, and I look forward to seeing more Texas-led advancements in the years to come.”Military-grade 3D packagingModern military applications rely on several discreet chips, which usually complicates these systems and makes them more expensive. The reason why jets or unmanned aerial vehicles use many chips is simple: each chip is responsible for a certain application (e.g., radar is one high-power chip made using GaN, aiming assistance is a typical high-performance made on an enhanced bulk silicon fabrication process) and is produced using a process technology that is best fit for this particular workload. The new project will attempt to build multi-chiplet designs that integrate different logic into one package and make that package as small as possible. As a result, these system-in-packages (SiP) will enable smaller, lighter military devices.  While most of the process technologies offered by companies like Intel, GlobalFoundries, or TSMC (now that it is in the U.S.) are good enough for many uses, some aerospace and military applications demand more rigidity, which is why specialized process technologies will still be in use for at least a while. Still, Intel’s 18A is going into some military applications, and this is just a start for the leading-edge nodes to enter this space.  Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox.When it comes to multi-chiplet packaging technologies, things are similar. Advanced packaging technologies must be aerospace and military-grade, and they do not look like ‘off-the-shelf’ methods from existing manufacturers that meet all of the U.S. DoC’s needs. This is where DARPA’s NGMM program, introduced in late 2023, comes in.SummaryWhile sophisticated multi-chiplet processors will enhance U.S. national security and global military leadership, the labs and manufacturing capability in Texas developed as part of the project will be accessible to developers and producers of civil applications too, which means a potential boost to the scientific innovation and the industrial might of the USA. […]

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TSMC establishes new Foundry 2.0 paradigm — could help address regulatory concerns of a monopoly

During its earnings call, TSMC proclaimed itself a ‘Foundry 2.0’ company to better reflect what it can offer to its customers and perhaps to defray anti-trust concerns from regulators. When it comes to self-branding, the company is also perhaps taking a page from Intel, which calls itself an integrated device manufacturer 2.0 (IDM 2.0). However, TSMC is much more than a contract chipmaker today. “At this time, we would like to expand our original definition of foundry industry to Foundry 2.0, which also includes packaging, testing, mask making, and others and all IDM, excluding memory manufacturing,” said C.C. Wei, chief executive and chairman of TSMC at the company’s earnings call with analysts and investors. “We believe this new definition better reflects TSMC’s expanding addressable market opportunities in the future.” Other concerns might be top of mind, too. Perhaps TSMC has rebranded itself as a ‘Foundry 2.0’ to avoid antitrust concerns. The foundry market is big, and TSMC owns around 61.2% of it, according to TrendForce. However, the mask-making and packaging markets are also huge, and TSMC’s presence in that market is relatively insignificant. As a result, under the Foundry 2.0 definition, TSMC’s market share drops to around 28%, which should please regulators. However, as was the case with Microsoft and browsers a couple of decades ago, regulators might not accept TSMC’s own definition of its addressable markets, which now includes everything from mask-making to packaging.Of course, there are plenty of other reasons for TSMC to justify the ‘Foundry 2.0’ positioning. When Morris Chang launched TSMC in 1987 (and essentially established the whole foundry industry), the company used equipment from the Industrial Technology Research Institute (ITRI) and a fabrication technology from Philips to process wafers for its very first customers, large companies like Intel, Motorola, Philips, or Texas Instruments. These companies could not only develop their own designs but also make their own photomasks and do assembly, testing, and packaging for their own products. All they needed from TSMC was its production capacity (which was several generations behind), as they did not want to use their own to build outdated products. Fast forward to today, TSMC can handle all aspects of chip production, print industry-leading photomasks, process wafers using nodes that are ahead of those available at IDMs like Intel, dice wafers, test individual dies, then package them using some of the most advanced packaging technologies available.  While large clients like AMD, Intel, and Nvidia have silicon specialists who can even optimize TSMC’s production nodes for particular products, many emerging companies do not have the engineering talent on their staff. Such companies would rather bring TSMC a .GDS file and expect their chip several months later, paying TSMC hefty sums for its services. Of course, TSMC would only handle advanced chip packaging, but it can also help find the right OSAT shop for its clients.  Of course, TSMC is not the only Foundry 2.0 company in the industry, as Intel Foundry can also offer vertically integrated services to its clients. However, companies like GlobalFoundries preferred to sell off their mask shops to third parties, focusing on the most lucrative side of the foundry business, but now missing a crucial part of the whole chip manufacturing flow. Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox.For TSMC, its Foundry 2.0-badged vertical integration of services means higher revenue in the coming years. For example, the company expects its 2024 revenue to be mid-20% higher than in 2023. It also expects growth to continue in the future.  […]

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Huawei sues MediaTek for patent infringement of unnamed technology

Huawei Technologies has filed a lawsuit against MediaTek for alleged patent infringement, reports Nikkei. The case was filed in a Chinese court and is believed to be one of Huawei’s efforts to increase its revenue by collecting licensing fees and royalties. Although MediaTek confirmed that Huawei had sued it, it did not reveal the nature of the allegations or which patents are involved. MediaTek is one of the world’s largest suppliers of application processors for smartphones and other types of consumer electronics. In fact, the company used to supply system-on-chips (SoCs) for some of Huawei’s own handsets. MediaTek’s clients include major consumer electronics brands like Amazon, Samsung, Oppo, Sony, Vivo, and Xiaomi. Many of MediaTek’s customers are either based in China or manufacture their devices in China, so banning sales of its processors in Tianxia would be devastating for MediaTek’s business in general. Details about the lawsuit, including the damages Huawei seeks, have not been made public.MediaTek confirmed the lawsuit in a filing with the Taiwan Stock Exchange, noting it would not significantly impact the company, but declined further comment.  Nikkei’s sources suggest Huawei’s lawsuit aims to collect royalties to fund ongoing research and development. Huawei possesses a substantial number of standard-essential patents, particularly in 5G technology, which holds about 20% of global patents. Since 2021, the company has intensified its efforts to collect royalties, forming licensing agreements with various European automakers such as BMW, Mercedes Benz, and VAG (Volkswagen Audi Group).  In 2022, Huawei earned $560 million from patent royalties. Around 200 companies, including Amazon, Samsung, and Oppo, currently pay for the use of its technologies. Huawei is not new to turning to litigation to collect royalties. The company sued T-Mobile in 2014, Samsung in 2016, and Verizon in 2020 over mobile connectivity patents. More recently, in 2022, Huawei sued Amazon and Netgear over its Wi-Fi 6 and Wi-Fi 5 patents. The company also sued Stellantis the same year to collect royalty fees for using its patents in cars such as Citroen, Fiat, Peugeot, and Opel.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]

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Micron unveils MRDIMMs for Intel Xeon 6: Up to 256GB DDR5-8800 modules

Micron Technology has introduced its new multiplexed rank dual inline memory modules (MRDIMMs) designed to combine high performance, low latency, high capacity, and predictable power consumption for next-generation Intel Xeon 6 server platforms. As the number of cores per socket rise, the new modules will be particularly useful to ensure decent per-core memory bandwidth, which will be valuable for artificial intelligence (AI) and high-performance computing (HPC) applications. MRDIMMs are JEDEC-standardized next-generation memory modules that essentially feature two DDR ranks that run in a multiplexed mode to double the speed. To enable such operation, the modules are equipped not only with more memory devices, but also with an MRCD chip that allows simultaneous access to both ranks and MDB chips that enable muxing and demuxing. The host CPU interacts with an MRDIMM module at an 8800 MT/s data transfer rate (for the first generation, the next generation expected to reach 12800 MT/s), but all the components on the module work at half the rate, enabling to tighter latencies and keeping power consumption of the module in check.  (Image credit: Micron)Lower latencies greatly increases the real-world performance of memory subsystems. Micron and Intel claim that a 128 GB DDR5-8800 MRDIMM can offer an up to 40% lower loaded latency than a 128 GB DDR5-6400 RDIMM. As for power consumption, keeping it in chip is important for modern server platforms as combined consumption of memory modules can be comparable or even higher than power consumption of some server CPUs. (Image credit: Micron)”Micron’s latest innovative main memory solution, MRDIMM, delivers the much-needed bandwidth and capacity at lower latency to scale AI inference and HPC applications on next-generation server platforms,” said Praveen Vaidyanathan, vice president and general manager of Micron’s Compute Products Group. “MRDIMMs significantly lower the amount of energy used per task while offering the same reliability, availability and serviceability capabilities and interface as RDIMMs, thus providing customers a flexible solution that scales performance. Micron’s close industry collaborations ensure seamless integration into existing server infrastructures and smooth transitions to future compute platforms.” (Image credit: Micron)Micron plans to offer a comprehensive line-up of DDR5-8000 and DDR5-8800 MRDIMMs in both standard and tall form factors (TFF) based on 16 Gb, 24 Gb, and 32 Gb DDR5 DRAM devices made using its proven 1β technology. Standard-height MRDIMMs will be available in 32 GB, 64 GB, 96 GB, 128 GB, and 256 GB density without using any 3D-stacked DRAM devices, which means higher performance, lower power, and lower costs. TFF MRDIMMs with a 56.9 mm height and aimed at over 1U servers will be available in 128 GB and 128 GB capacities. Tall form-factor MRDIMMs have a larger surface area compared to standard-sized modules, which, for the same airflow, results in a 24% lower temperature. This design reduces the likelihood of thermal throttling and enhances energy efficiency, making them particularly suitable for AI and HPC machines. Upcoming MRDIMMs from Micron and other suppliers (including both first-party makers like Samsung and SK Hynix and third-party suppliers like Adata) are set to be compatible with Intel’s Xeon 6 platforms. On the software side of matters, DDR5 MRDIMMs do not require any software development or turning, though expect large server OEMs like Dell, HPE, and Lenovo to run comprehensive tests to ensure compatibility and stable performance across hundreds of workloads. Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox.Micron’s MRDIMMs are currently sampling and are expected to ship in volume in the latter half of 2024. Subsequent generations promise even greater performance, with up to 45% better memory bandwidth per channel – at 12800 MT/s — compared to current RDIMMs at 6400 MT/s.  […]

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China memory maker YMTC sues Micron in the US — accuses Micron of infringing 11 of its patents

Chinese 3D NAND champion YMTC has filed a lawsuit against Micron in the Northern District of California (via Blocks & Files) accusing the American company of infringing 11 of its patents covering various aspects of 3D NAND operation. Yangtze Memory asks the court to order Micron to stop the stop the sale of Micron’s memory in the U.S. while awarding it with royalty fees. YMTC says that Micron’s 3D NAND memory with 96 layers (B27A), 128 layers (B37R), 176 layers (B47R), and 232 layers (B58R) as well as some of Micron’s DDR5 SDRAM products (Y2BM-series) infringe 11 of its patents or patents applications filed in the U.S. The list of patent applications gathered by @lithos_graphein indicates that they cover general aspects of 3D NAND and DRAM functionality, which may essentially mean that YMTC is trying to make Micron’s life harder in a get to gain a leverage against the U.S. government. The U.S. Department of Commerce blacklisted YMTC in late 2022, which made it considerably harder for the company to obtain advanced fab equipment from American companies to build its market-leading 3D NAND devices. Last year the company faced even larger problems when the DoC barred sales of fab tools and technologies that could be used to build 3D NAND with more than 128 active layers, which was another blow for the company. But Yangtze Memory has managed to persuade Chinese Cybersecurity Review Office to ban the use of Micron’s memory in PCs used by government agencies as well as local governments. Despite severe restrictions set by the U.S. government, YMTC continued to evolve its 3D NAND memory. The company’s Xtacking 3.0 flash memory is in mass production (and some of such devices even do not infringe U.S. sanctions) and now the company is working on 3D NAND featuring its Xtacking 4.0 architecture. Also, earlier this year the company said that it had managed to dramatically improve endurance of 3D QLC NAND to a level of 3D TLC NAND (to 4,000 program/erase cycles), which significantly improves characteristics of inexpensive SSDs. Interestingly, U.S.-based Patriot Memory is prepping a high-end PCIe Gen5 x4 SSD with an up to 14 GB/s read speed based on a controller from Maxiotek (a China-based company that evolved from JMicron) and 3D NAND memory from YMTC.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]

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AMD’s biggest AI GPU booster adds support for Nvidia, too — Lamini AI preps memory tuning for Nvidia hardware

Lamini AI was among the first companies to obtain AMD’s Instinct MI300X AI chips and has gained fame for being an all-AMD AI shop, a rarity in an Nvidia-dominated world. The CEO has even roasted Nvidia over its GPU shortages, highlighting that the company already had AMD GPUs in stock. However, it looks like one cannot really ignore the market leader when it controls the lion’s share of the AI hardware market, so this month, Lamini AI announced that it would optimize its software stack for Nvidia hardware as well. “Really looking forward to collaborating and partnering with Nvidia to further optimize our stack on Nvidia hardware,” wrote Sharon Zhou, the founder and chief executive of Lamini AI, in an X post. When asked to clarify the company’s stance on AMD’s hardware, Zhou indicated that while Lamini AI has collaborated with AMD, the partnership is not exclusive. Furthermore, the company is also open to working with other hardware providers. In fact, Zhou even said that collaborations with other hardware developers might be good for AMD as it might eventually lead certain end users with Nvidia GPUs to migrate to AMD Instinct. Just grilling up some GPUs 💁🏻‍♀️Kudos to Jensen for baking them first https://t.co/4448NNf2JP pic.twitter.com/IV4UqIS7ORSeptember 26, 2023″We are partnered with AMD — they are incredible — I fully believe in Lisa,” the head of Lamini AI responded. “The partnership is deep and not exclusive. It’s hard to see from the outside, but strategically this helps us deploy to more customers who already have Nvidia GPUs and from there help them get onto AMD GPUs without code changes as well. Hope we will be partnering with even more compute providers in the future.” Lamini AI is an enterprise platform designed to help organizations develop, fine-tune, and deploy large language models (LLMs) efficiently. The platform offers a comprehensive solution for managing the entire lifecycle of LLMs, from model selection and tuning to deployment and inference. For example, with advanced memory tuning techniques, Lamini ensures over 95% factual accuracy, significantly reducing hallucinations and enhancing the reliability of its models. Also, Lamini AI’s high-performance capabilities allow it to handle up to 52 times more queries per second compared to other solutions, reducing latency and improving user experience. Given the specialization of Lamini AI, it is pretty hard for the company to ignore Nvidia’s hardware, as the majority of its potential clients might believe that Nvidia’s H100 and H200 GPUs are the best fit for their workloads. To that end, the platform supports deployment on various environments, including on-premise, private data centers, and public clouds, and is compatible with both AMD and Nvidia GPUs (although the company made jokes about Nvidia’s GPUs in the past). It is noteworthy that the company’s chief technology officer, Greg Diamos, is a former Nvidia CUDA software architect, so the company has some experience with CUDA.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]

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The U.S. is building a chip packaging supply chain in Latin America

To reduce dependency on Asia and package American chips in the Americas, the U.S. government has launched an initiative to boost chip packaging capabilities in Latin America. Notably, Intel already has an assembly, testing, and packaging facility in San Jose, Costa Rica. Yet, it is unclear whether the blue giant will benefit from the new initiative.Meanwhile, the statement on the initiative’s website stresses enhancing semiconductor manufacturing and securing supply chains; the initiative aims to prevent any single country or region from monopolizing the crucial chip packaging sector, which is vital to avoid potential manipulation or disruption of these essential services.One of the things about the U.S. government’s CHIPS & Science Act initiative is that while there will be more semiconductors products in America by the end of the decade, most of them would have to be packaged outside of the U.S., somewhere in Asia, which complicates the whole supply chain.The U.S. Department of State and the Inter-American Development Bank (IDB) have launched the CHIPS ITSI Western Hemisphere Semiconductor Initiative to enhance semiconductor assembly, testing, and packaging (ATP) capabilities in key partner countries: Mexico, Panama, and Costa Rica. The program will support public-private partnerships and the adoption of OECD (Organisation for Economic Co-operation and Development) recommendations to develop robust semiconductor ecosystems in the said countries.Under the terms of the program, the ITSI Fund will provide $500 million over five years starting in fiscal year 2023. Each year, $100 million will be allocated to ‘to promote the development and adoption of secure and trustworthy telecommunications networks and ensure semiconductor supply chain security and diversification,’ which indicates that in addition to semiconductor ATP capabilities, the initiative will also address the development of telecommunication networks. It aligns with ongoing IDB efforts to boost regional semiconductor supply chain competitiveness through the Americas Partnership for Economic Prosperity.”The ultimate goal is to bring new trusted information and communications technology vendors and semiconductor production capacity into the global market, in ways that will directly benefit the United States as well as our allies and partners,” a statement on the initiative’s website reads.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]

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U.S. planning ‘draconian’ sanctions against China’s semiconductor industry: Report

The U.S. government is considering implementing more severe restrictions on China’s access to advanced chip making tools, which some of the country’s allies reportedly call ‘draconian,’ reports Bloomberg. Key proposals include applying the Foreign Direct Product Rule (FDPR), pressuring allies to limit service and repair of equipment in China, and broadening the unverified list requiring licenses for certain technologies. These measures aim to hinder advancements of China’s semiconductor industry. One key proposal is the application of the Foreign Direct Product Rule (FDPR), which would allow the U.S. to exert control over foreign-produced items that contain any American technology. This would particularly impact companies like Tokyo Electron and ASML, restricting their ability to provide China with advanced wafer fab equipment (WFE). This measure is seen as ‘draconian’ by U.S. allies, but it reflects the administration’s determination to restrict China’s chipmaking progress. Additionally, the U.S. is urging its allies, including Japan and the Netherlands, to impose stricter limits on their companies capabilities to service and repair semiconductor equipment already delivered to China. Again, if enacted, this will primarily impact ASML and Tokyo Electron. This measure aims to prevent Chinese chipmakers, such as SMIC, from maintaining or upgrading their equipment using foreign assistance, thereby stalling their progress in developing more advanced nodes and producing chips on sophisticated process technologies. Further sanctions on specific Chinese semiconductor companies are also under consideration. These additional measures would tighten existing controls and increase the pressure on China’s chipmakers. The U.S. government wants to ensure that Chinese firms have limited access to critical technology, thereby hindering their ability to advance in the semiconductor industry. Another strategy involves expanding the criteria for the unverified list. This list requires companies to obtain licenses for shipping certain restricted technologies. By broadening this list, the U.S. aims to signal that firms continuing to serve Chinese customers deemed security risks might face additional controls, which could prevent Chinese companies from circumventing current restrictions by relying on foreign equipment and expertise. The U.S. WFE industry has voiced concerns that current export restrictions unfairly harm American companies while not irrecoverably hindering Chinese progress. Yet, companies like Applied Materials, KLA, and LAM Research argue that the proposed FDPR and other measures could lead to non-cooperation from allies and incentivize global firms to exclude U.S. technology from their supply chains. The American makers of fab equipment are reportedly advocating for expanding the criteria for the so-called unverified list to prevent Chinese firms from bypassing existing controls.But while these measures aim to hinder China’s technological advancements and to some degree protect American technologies from being copied by Chinese companies, they also pose significant economic challenges and risks for U.S. and allied companies as they too can lose sales due to U.S. curbs against China.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]

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Intel reportedly prepping three Panther Lake configurations, for laptops after Lunar Lake

Intel yet has to commercially release its codenamed Arrow Lake and Lunar Lake processors, but hardware leakers are already disclosing the company’s plans concerning next-gen Panther Lake processors, expected in late 2025 at the earliest. Intel is apparently prepping three general configurations of its Panther Lake CPUs, according to Jaykihn, a blogger who seemingly has access to samples of Intel’s next-generation processors and documentation covering forthcoming CPUs. Keep in mind that we are dealing with a leak, so take all of this info with the usual serving of salt. The three rumored Panther Lake base configurations are the following:Panther Lake-U: up to four high-performance cores, up to four ultra-low-power cores, and up to four Xe graphics clusters. These CPUs will have a processor base power of 15W, which is in-line with contemporary thin-and-light notebook processors.Panther Lake-H: up to four high-performance cores, up to eight energy-efficient cores, up to four ultra-low-power cores, and up to four Xe GPU clusters. These processors will increase their PBP to 25W and will address higher-end laptops.The even higher-performing Panther Lake-H is expected to pack up to four high-performance cores, up to eight energy-efficient cores, up to four ultra-low-power cores, and up to 12 Xe graphics clusters to provide decent performance in games. These CPUs are also projected to feature a PBP of 25W.From a hardware and chipmaking standpoint, Intel’s Panther Lake-U/H processors will consist of three dies: a compute, a graphics, a PCD (platform connectivity hub), and two passive dies for rigidity. We do not yet know which process technologies these CPUs will utilize at this point, though it is likely that the compute die will be made on Intel’s 18A (1.8nm-class) and the system-in-package will be assembled by Intel in the USA. That’s pure speculation, though. If the information from the blogger is accurate, then Panther Lake-U will have up to eight cores, whereas Panther Lake-H processors will sport up to 16 cores. It’s close to impossible to tell how these CPUs will stack up against Meteor Lake, Arrow Lake, and Lunar Lake in terms of performance. But based on what we do know about Intel’s Panther Lake-U, these processors are set to become available in Q4 2025, whereas Intel’s Panther Lake-H are expected to hit the market in Q1 2026.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]

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New SCALE tool enables CUDA applications to run on AMD GPUs

Spectral Compute has introduced SCALE, a new toolchain that allows CUDA programs to run directly on AMD GPUs without modifications to the code, reports Phoronix. SCALE can automatically compile existing CUDA code for AMD GPUs, which greatly simplifies transition of software originally developed for Nvidia hardware to other platforms without breaking any end user license agreements.  Spectral’s SCALE is a toolkit, akin to Nvidia’s CUDA Toolkit, designed to generate binaries for non-Nvidia GPUs when compiling CUDA code. It strives for source compatibility with CUDA, including support for unique implementations like inline PTX as, and nvcc’s C++ implementation, though it can generate code compatible with AMD’s ROCm 6. One of SCALE’s significant advantages is its ability to act as a drop-in replacement for Nvidia’s own nvcc compiler. Therefore, unlike other projects that translate CUDA code to another language or use other manual steps, SCALE directly compiles CUDA sources for AMD GPUs.  SCALE’s implementation leverages some open-source LLVM components to create a solution that is both efficient and user-friendly as the software package aims to offer a more seamless and integrated solution that ZLUDA, which is a translation layer that is prohibited to use. It even mimics the Nvidia CUDA Toolkit runtime, making it easier for developers to port their existing CUDA programs to AMD hardware. SCALE has undergone extensive testing with a variety of software, including Blender, Llama-cpp, XGboost, FAISS, GOMC, STDGPU, Hashcat, and Nvidia Thrust, and has proven that it works stably and correctly. Testing has been conducted on RDNA 2 and RDNA 3 GPUs, with basic testing on RDNA 1 and ongoing development for Vega support. The developers did not have access to AMD’s CDNA-based GPUs though.The lack of support for CDNA-based processors is a disadvantage of SCALE because datacenter software designed using CUDA and for CUDA-compatible hardware dominates the rapidly growing AI space and many developers are interested in easily porting their programs to competing platforms, expanding their addressable market. Funding for SCALE has been provided by Spectral Compute’s consulting business since 2017, without financial backing from AMD. Although the program is not open source, there is a Free Edition License available and this one can be used for commercial applications.Get Tom’s Hardware’s best news and in-depth reviews, straight to your inbox. […]