TSMC will boost its chip-on-wafer-on-substrate (CoWoS) packaging capacity in reaction to skyrocketing demand from major clients like Nvidia, Apple, AMD, Broadcom, and Marvell. A report published by UDN today says the contract chipmaker will increase next year’s monthly CoWoS production targets by 20%, to 35,000 wafers per month.
In September we reported that Nvidia AI GPU shortages could persist for a year and a half due to a lack of CoWoS production capacity at TSMC. Since then, several other major chip designers have apparently been struggling to place sufficient CoWoS orders to fuel their advanced processor ambitions.
Lifting CoWoS production capacity by 20% might be just enough for the not-too-distant future. In September, chairman of TSMC Mark Liu told Nikkei that his firm was trying to support customer CoWoS demand but was only managing to “support about 80%,” of potential orders.
Probably the most important processors to Nvidia which require CoWoS packaging technology to integrate processing cores and HBM memory are its A100 and H100 (and, soon, H200) compute GPUs. The source asserts that Nvidia’s data center GPUs eat up the largest chunk of CoWoS capacity, accounting for about 60% of total output.
A report on the same topic published by the Commercial Times provides a longer-term outlook for TSMC’s CoWoS plans. While in the short term, TSMC must be commended for expanding its production capacity by 20%, it will “double CoWoS production capacity by the end of 2024,” according to a quote attributed to TSMC’s CEO, CC Wei.
Boosting CoWoS capacity isn’t entirely within TSMC’s realm of control, though. The firm has to encourage increased production by its materials suppliers to expand at the rate it intends to. This is, or was, a major pinch point in CoWoS output expansion plans, according to a financial analyst meeting with Wei in October.